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9fg1901h idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 frequency gearing clock for cpu, pci e gen1 & fbd da t asheet 1 ? description the 9fg1901h follows the intel db1900g differential buffer specification. this b uff er pro vides 19 output cloc ks f or cpu host bus , pci-express , or fully buff ered dimm applications . the outputs are configured with two groups. both groups, dif_(16:0) anddif_(18:17) can be equal to or have a gear ratio to the input clock. a diff erential cpu cloc k from a ck410b+ main cloc k gener ator , such as the ics932s421, dr iv es the ics9fg1901. the 9fg1901h can provide outputs up to 400mhz. ke y specifications ? dif output cycle-to-cycle jitter < 50ps ? dif output-to-output skew across all outputs in 1:1 mode < 150ps features/benefits? pow er up def ault is all outputs in 1:1 mode ? dif_(16:0) can be ?gear-shifted? from the input cpu host cloc k ? dif_(18:17) can be ?gear-shifted? from the input cpu host cloc k ? spread spectrum compatible ? suppor ts output cloc k frequencies up to 400 mhz ? 8 selectab le smbus addresses ? smbus address deter mines pll or bypass mode ? vdd a controlled po w er do wn mode functional block diagram stop logic clk_in clk_in# dif(16:0) control logic high_bw# smb_a2_pllbyp# smbdat smbclk spread compatible pll 17 iref oe(16:5)#,oe_01234# 13 smb_a0 smb_a1 fs_a_410 stop logic dif(18:17) 2 oe_17_18# gear shift logic spread compatible pll gear shift logic
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 2 pin configuration 72-pin mlf po wer do wn functionality functionality at p o wer up (pll mode) po wer gr oups vdda/pd# clk_in/clk_in# dif dif# 3.3v (nom) running on gnd x off functionality note it is recommended that byte 2, bit 6 be toggled fro m 1 to 0 and back to 1, the first time vdda is applied. thi s ensures proper initialization of the device. hi-z inputs outputs pll state running fs_a_410 1 clk_in (cpu fsb) mhz dif(18:0) mhz 1 100 <= clk_in < 200 clk_in 0 200<= clk_in <= 400 clk_in 1. fs_a_410 is a low-threshold input. please see t he v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. vdd gnd 3 2 main pll, analog 11,27,47,63 10,28,46,64 dif clocks description pin number smb_a2_pllbyp# clk_in# clk_in oe17_18# dif_18# dif_18 dif_17# dif_17 gnd vdd dif_16# dif_16 oe16# dif_15# dif_15 oe15# dif_14# dif_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 iref 1 54 oe14# gnda 2 53 dif_13# vdda/pd# 3 52 dif_13 high_bw# 4 51 oe13# fs_a_410 5 50 dif_12# dif_0 6 49 dif_12 dif_0# 7 48 oe12# dif_1 8 47 vdd dif_1# 9 46 gnd gnd 10 45 dif_11# vdd 11 44 dif_11 dif_2 12 43 oe11# dif_2# 13 42 dif_10# dif_3 14 41 dif_10 dif_3# 15 40 oe10# dif_4 16 39 dif_9# dif_4# 17 38 dif_9 oe_01234# 18 37 oe9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 smbclk smbdat oe5# dif_5 dif_5# oe6# dif_6 dif_6# vdd gnd oe7# dif_7 dif_7# oe8# dif_8 dif_8# smb_a0 smb_a1 9fg1901
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 3 pin description pin # pin name pin type description 1 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is t he standard value. 2 gnda pwr ground pin for the pll core. 3 vdda/pd# pwr 3.3v power for the pll core that also functions as power down. collapsing this power supply places the device in power down m ode. 4 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 5 fs_a_410 in 3.3v tolerant low threshold input for cpu frequenc y selection. this pin requires ck410 fsa. refer to input electrical chara cteristics for vil_fs and vih_fs threshold values. 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complement clock output 8 dif_1 out 0.7v differential true clock output 9 dif_1# out 0.7v differential complement clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_2 out 0.7v differential true clock output 13 dif_2# out 0.7v differential complement clock outpu t 14 dif_3 out 0.7v differential true clock output 15 dif_3# out 0.7v differential complement clock outpu t 16 dif_4 out 0.7v differential true clock output 17 dif_4# out 0.7v differential complement clock outpu t 18 oe_01234# in active low input for enabling dif pairs 0, 1, 2, 3 and 4. 1 = tri-state outputs, 0 = enable outputs 19 smbclk in clock pin of smbus circuitry, 5v tolerant 20 smbdat i/o data pin of smbus circuitry, 5v tolerant 21 oe5# in active low input for enabling dif pair 5. 1 = tri-state outputs, 0 = enable outputs 22 dif_5 out 0.7v differential true clock output 23 dif_5# out 0.7v differential complement clock outpu t 24 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 25 dif_6 out 0.7v differential true clock output 26 dif_6# out 0.7v differential complement clock outpu t 27 vdd pwr power supply, nominal 3.3v 28 gnd pwr ground pin. 29 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 30 dif_7 out 0.7v differential true clock output 31 dif_7# out 0.7v differential complement clock outpu t 32 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 33 dif_8 out 0.7v differential true clock output 34 dif_8# out 0.7v differential complement clock outpu t 35 smb_a0 in smbus address bit 0 (lsb) 36 smb_a1 in smbus address bit 1
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 4 pin description (contin ued) pin # pin name pin type description 37 oe9# in active low input for enabling dif pair 9. 1 = tri-state outputs, 0 = enable outputs 38 dif_9 out 0.7v differential true clock output 39 dif_9# out 0.7v differential complement clock outpu t 40 oe10# in active low input for enabling dif pair 10. 1 = tri-state outputs, 0 = enable outputs 41 dif_10 out 0.7v differential true clock output 42 dif_10# out 0.7v differential complement clock outp ut 43 oe11# in active low input for enabling dif pair 11. 1 = tri-state outputs, 0 = enable outputs 44 dif_11 out 0.7v differential true clock output 45 dif_11# out 0.7v differential complement clock outp ut 46 gnd pwr ground pin. 47 vdd pwr power supply, nominal 3.3v 48 oe12# in active low input for enabling dif pair 12. 1 = tri-state outputs, 0 = enable outputs 49 dif_12 out 0.7v differential true clock output 50 dif_12# out 0.7v differential complement clock outp ut 51 oe13# in active low input for enabling dif pair 13. 1 = tri-state outputs, 0 = enable outputs 52 dif_13 out 0.7v differential true clock output 53 dif_13# out 0.7v differential complement clock outp ut 54 oe14# in active low input for enabling dif pair 14. 1 = tri-state outputs, 0 = enable outputs 55 dif_14 out 0.7v differential true clock output 56 dif_14# out 0.7v differential complement clock outp ut 57 oe15# in active low input for enabling dif pair 15. 1 = tri-state outputs, 0 = enable outputs 58 dif_15 out 0.7v differential true clock output 59 dif_15# out 0.7v differential complement clock outp ut 60 oe16# in active low input for enabling dif pair 16. 1 = tri-state outputs, 0 = enable outputs 61 dif_16 out 0.7v differential true clock output 62 dif_16# out 0.7v differential complement clock outp ut 63 vdd pwr power supply, nominal 3.3v 64 gnd pwr ground pin. 65 dif_17 out 0.7v differential true clock output 66 dif_17# out 0.7v differential complement clock outp ut 67 dif_18 out 0.7v differential true clock output 68 dif_18# out 0.7v differential complement clock outp ut 69 oe17_18# in active low input for enabling dif pairs 17 and 18. 1 = tri-state outputs, 0 = enable outputs 70 clk_in in true input for differential reference clo ck. 71 clk_in# in complement input for differential refere nce clock. 72 smb_a2_pllbyp# in smbus address bit 2. when low, the part operates as a fanout buffer with the pll bypassed. when high, the part operates as a zer o-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll u sed)
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 5 bit 3 bit 2 bit 1 bit 0 200.0 266.7 320.0 333.3 400.0 0 0 0 0 0 3 1 0.333 66.7 88.9 106.7 111.1 133.3 0 0 0 0 1 5 2 0.400 80.0 106.7 128.0 133.3 160.0 0 0 0 1 0 12 5 0.417 83.3 111.1 133.3 138.9 166.7 0 0 0 1 1 2 1 0.500 100.0 133.3 160.0 166.7 200.0 0 0 1 0 0 5 3 0.600 120.0 160.0 192.0 200.0 240.0 0 0 1 0 1 8 5 0.625 125.0 166.7 200.0 208.3 250.0 0 0 1 1 0 3 2 0.667 133.3 177.8 213.3 222.2 266.7 0 0 1 1 1 4 3 0.750 150.0 200.0 240.0 250.0 300.0 0 1 0 0 0 6 5 0.833 166.7 222.2 266.7 277.8 333.3 0 1 0 0 1 1 1 1.000 200.0 266.7 320.0 333.3 400.0 0 1 0 1 0 5 6 1.200 240.0 320.0 384.0 400.0 na 0 1 0 1 1 4 5 1.250 250.0 333.3 400.0 na na 0 1 1 0 0 3 4 1.333 266.7 355.6 na na na 0 1 1 0 1 2 3 1.500 300.0 400.0 na na na 0 1 1 1 0 3 5 1.667 333.3 na na na na 0 1 1 1 1 1 2 2.000 400.0 na na na na 100 133.33 160 166.67 1 0 0 0 0 3 1 0.333 1 0 0 0 1 5 2 0.400 na 53.3 64.0 66.7 1 0 0 1 0 12 5 0.417 na 55.6 66.7 69.4 1 0 0 1 1 2 1 0.500 50.0 66.7 80.0 83.3 1 0 1 0 0 5 3 0.600 60.0 80.0 96.0 100.0 1 0 1 0 1 8 5 0.625 62.5 83.3 100.0 104.2 1 0 1 1 0 3 2 0.667 66.7 88.9 106.7 111.1 1 0 1 1 1 5 4 0.800 80.0 106.7 128.0 133.3 1 1 0 0 0 6 5 0.833 na 111.1 133.3 138.9 1 1 0 0 1 1 1 1.000 100.0 133.3 160.0 166.7 1 1 0 1 0 5 6 1.200 120.0 160.0 192.0 200.0 1 1 0 1 1 4 5 1.250 125.0 166.7 200.0 208.3 1 1 1 0 0 3 4 1.333 133.3 177.8 213.3 222.2 1 1 1 0 1 2 3 1.500 150.0 200.0 1 1 1 1 0 3 5 1.667 166.7 222.2 266.7 277.8 1 1 1 1 1 1 2 2.000 200.0 266.7 320.0 333.3 shaded areas are shown for reference only and devic e operation is not guaranteed output (n) gear ratio (n/m) smbus byte 0 9fg1901 programmable gear ratios fs_a_410 input (cpu fsb) and output frequencies (mhz) input (m) note: lines in bold are power-up defaults for fs_a_410 = 0 and 1 respe ctively. clk in (cpu fsb) frequency (mhz)
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 6 9fg1901 smbus address mapping when using ck410b+, 9fg1201, and 9db401/801 smb adr: dc 9db401/801 (db400/800) smb adr: d2 9324201 (ck410b+) pll bypass mode smb_a2_pllbyp# = 0 pll zdb mode smb_a2_pllbyp# = 1 smb_a(2:0) = 100 smb adr: d8 smb_a(2:0) = 101 smb adr: da smb_a(2:0) = 110 smb adr: dc smb_a(2:0) = 111 smb adr: de smb_a(2:0) = 000 smb adr: d0 9fg1901 (db1900g) smb_a(2:0) = 001 smb adr: d2 smb_a(2:0) = 010 smb adr: d4 smb_a(2:0) = 011 smb adr: d6 9fg1901 (db1900g) 9fg1901 (db1900g) 9fg1901 (db1900g) 9fg1901 (db1900g) 9fg1901 (db1900g) 9fg1901 (db1900g) 9fg1901 (db1900g) smb_a(2:0) = 100 smb adr: d8 9fg1201/2 (db1200g) smb_a(2:0) = 101 smb adr: da 9fg1201/2 (db1200g) smb_a(2:0) = 110 smb adr: dc 9fg1201/2 (db1200g) smb_a(2:0) = 111 smb adr: de 9fg1201/2 (db1200g) smb_a(2:0) = 000 smb adr: d0 9fg1201/2 (db1200g) smb_a(2:0) = 001 smb adr: d2 9fg1201/2 (db1200g) smb_a(2:0) = 010 smb adr: d4 9fg1201/2 (db1200g) smb_a(2:0) = 011 smb adr: d6 9fg1201/2 (db1200g) or or or or or or or or or or
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 7 general smbus serial interface information for the 9fg1901h ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d0 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read:? controller (host) will send star t bit. ? controller (host) sends the write address d0 (h) ? ics clock will acknowledge ? controller (host) sends the begining bytelocation = n ? ics clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d1 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d0 (h) * beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d1 (h) * index block read operation slave address d0 (h) * beginning byte = n ack ack * note: see smbus address mapping (page 6), for programming smbus read/write address
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 8 smbustable: fsb frequency select register pin # name control function type 0 1 pwd bit 7 grsel_17 group of 17 gear ratio select rw gear ratio 1: 1 1 bit 6 grsel_2 group of 2 gear ratio select rw gear ratio 1:1 1 bit 5 x bit 4 rw latch bit 3 fsbg_3 fsb gear ratio fs_3 rw x bit 2 fsbg_2 fsb gear ratio fs_2 rw 0 bit 1 fsbg_1 fsb gear ratio fs_1 rw x bit 0 fsbg_0 fsb gear ratio fs_0 rw 1 smbustable: output control register pin # name control function type 0 1 pwd bit 7 dif_7 output control rw hi-z enable 1 bit 6 dif_6 output control rw hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control rw hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output and pll bw control register pin # name control function type 0 1 pwd bit 7 rw high bw low bw 1 bit 6 rw bypass pll 1 bit 5 dif_13 output control rw hi-z enable 1 bit 4 dif_12 output control rw hi-z enable 1 bit 3 dif_11 output control rw hi-z enable 1 bit 2 dif_10 output control rw hi-z enable 1 bit 1 dif_9 output control rw hi-z enable 1 bit 0 dif_8 output control rw hi-z enable 1 note: bit 7 is wired or to the high_bw# input, any 0 selects high bw note: bit 6 is wired or to the smb_a2_pllbyp# input , any 0 selects fanout bypass mode smbustable: output enable readback register pin # name control function type 0 1 pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x readback readback readback readback - oe_01234# input readback readback - oe5# input readback - oe6# input readback readback see note pll_bw# adjust readback - oe7# input - - - byte 1 byte 0 dif(16:0) dif(18:17) fs_a_410 latched input - reserved see ics9fg1901 programmable gear ratios table - 8 72 readback - oe9# input readback - oe8# input see note bypass# test mode / pll byte 3 byte 2 readback - high_bw# in readback readback - smb_a2_pllbyp# in readback
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 9 smbustable: output enable readback register pin # name control function type 0 1 pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x smbustable: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function type 0 1 pwd bit 7 rw 1 bit 6 rw 0 bit 5 rw 0 bit 4 rw 1 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 1 smbustable: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 69 readback 54 51 48 43 40 - readback - oe17_18# input readback device id 2 reserved device id 1 reserved readback readback readback device id 3 readback - oe13# input writing to this register configures how many bytes will be read back. - - -- - - -- - -- - -- device id 4 - reserved readback - oe14# input readback readback - oe10# input device id 5 reserved device id 0 57 byte 7 - - - - -- - byte 5 - byte 6 60 byte 4 device id 6 reserved readback - oe16# input device id 7 (msb) readback - oe12# input vendor id readback - oe11# input readback readback - oe15# input readback reserved reserved revision id reserved
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 10 smbustable: control pin readback register pin # name control function type 0 1 pwd bit 7 r x bit 6 x bit 5 x bit 4 dif_18 output control rw hi-z enable 1 bit 3 dif_17 output control rw hi-z enable 1 bit 2 dif_16 output control rw hi-z enable 1 bit 1 dif_15 output control rw hi-z enable 1 bit 0 dif_14 output control rw hi-z enable 1 smbustable: 1:1 pll operating set point register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 rw x bit 1 rw 1 bit 0 rw latch reserved reserved reserved reserved frequency select c see ics9fg1901h 1:1 pll programming table frequency select b fs_a_410 byte 9 - - - reserved byte 8 5 readback - fs_a_410 readback reserved reserved byte 9, bit 2 fsc byte 9, bit 1 fsb byte 9, bit 0 fs_a_410 clk_in (cpu fsb) mhz 1:1 dif outputs mhz notes 1 0 1 100.00 100.00 3 0 0 1 133.33 133.33 3 0 1 1 166.67 166.67 1 0 1 0 200.00 200.00 3 0 0 0 266.67 266.67 3 1 0 0 333.33 333.33 3 1 0 400.00 400.00 2 1 1 1 notes:fs_a_410 = 1 1. powerup default for fs_a_410 = 1 2. powerup default for fs_a_410 = 0 3. setting the exact fsb frequency after power is r equired to meet phase jitter specs. reserved 9fg1901h 1:1 pll programming
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 11 absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a gnd - 0.5 v dd + 0.5v v 1 3.3v logic supply voltage vdd_in gnd - 0.5 v dd + 0.5v v 1 storage temperature ts -65 150 c 1 ambient operating temp tambient 0 70 c 1 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1 electrical characteristics - input/supply/common ou tput parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5%, except clk_in 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5%, except clk_in v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua input low current i il1 v in = 0 v; inputs with no pull- up resistors -5 ua low threshold input- high voltage v ih_fs 3.3 v +/-5%, applies to fs_a_410 pin 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5%, applies to fs_a_410 pin v ss - 0.3 0.35 v 1 operating current i dd3.3op all outputs driven 600 ma 1 powerdown current i dd3.3pd all differential pairs tri-stated 36 ma 1 input frequency f i v dd = 3.3 v 100 400 mhz 3 pin inductance l pin 7 nh 1 c in logic inputs 6 pf 1 c out output pin capacitance 5 pf 1 clk stabilization t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd# dif output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v max maximum input voltage 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 input capacitance
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 12 electrical characteristics - dif 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 , r p =49.9 , ref = 475 parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max voltage vovs 1150 1 min voltage vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t jcyc-cyc pll mode, from differential wavefrom 50 ps 1,4,5 t jbyp bypass mode as additive jitter 50 ps 1,4 notes: 1.guaranteed by design and characterization, not 10 0% tested in production. 3.iref = vdd/(3xrr). for rr = 475 (1%), iref = 2.32ma. ioh = 6 x iref and voh = 0.7v @ zo=50 . 4. measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding input. 5. measured from differential cross-point to different ial cross-point 6. all bypass mode input-to-output specs refer to t he timing between an input edge and the specific ou tput edge created by it. jitter, cycle to cycle 2. all long term accuracy and clock period specifica tions are guaranteed assuming that the input freque ncy meets ck410b accuracy requirements absolute min period t absmin statistical measurement on single ended signal using oscilloscope math function. mv average period tperiod measurement on single ended signal using absolute value. mv
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 13 electrical characteristics - skew and differential jitter parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% group parameter description min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode (1:1 only), nominal value @ 25 c , 3 . 3 v -500 270 500 ps 1,2,4,5,8, 12 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode (1:1 only), nominal value @ 25 c , 3 . 3 v 2.5 3.8 4.5 ns 1,2,3,5, 12 clk_in, dif [x:0] ? t spo_pll input-to-output skew variation in pll mode (over specified voltage / temperature operating ran ges) 270 |500| ps 1,2,4,5,6, 10,12 clk_in, dif [x:0] ? t pd_byp input-to-output skew variation in bypass mode (over specified voltage / temperature operating ran ges) 467 |500| ps 1,2,3,4,5, 6,10,12 dif[18:17] t skew_g2 output-to-output skew group of 2 (common to bypass and pll mode) 10 50 ps 1,2,12 dif[16:0] t skew_g17 output-to-output skew group of 17 (common to bypass and pll mode) 70 100 ps 1,2,12 dif[18:0] t skew_a19 output-to-output skew across all 19 outputs (common to bypass and pll mode - all outputs at same gear) 70 150 ps 1,2,3,12 dif[18:0] t jph differential phase jitter (rms value) 5 10 ps 1,4,7,12 dif[18:0] t ssterror differential spread spectrum tracking error (peak t o peak) 40 80 ps 1,4,9,12 pll jitter peaking j peak-hibw (high_bw# = 0) 0 2.2 2.5 db 11,12 pll jitter peaking j peak-lobw (high_bw# = 1) 0 1.4 2 db 11,12 pll bandwidth pll hibw (high_bw# = 0) 2 3.7 4 mhz 12,13 pll bandwidth pll lobw (high_bw# = 1) 0.7 1.2 1.4 mhz 12,13 notes on skew and differential jitter parameters: 8. t is the period of the input clock 11. measured as maximum pass band gain. at frequencies w ithin the loop bw, highest point of magnification is called pll jitter peaking. 12. guaranteed by design and characterization, not 100% tested in production. 13. measured at 3 db dow n or half pow er point. 3. all bypass mode input-to-output specs refer to the timing between an input edge and the specific o utput edge created by it. 4. this parameter is deterministic for a given devi ce 1. measured into fixed 2 pf load cap. input to ou tput skew is measured at the first output edge foll owing the corresponding input. 2. measured from differential cross-point to diffe rential cross-point 10. this parameter is an absolute value. it is not a double-sided figure. 9. differential spread spectrum tracking error is t he difference in spread spectrum tracking betw een t w o 9fg1901h devices this parameter is measured at the outputs of tw o separate 9fg1901h devices driven by a single ck410b+ in spread spectrum mode. the 9fg1 901h must set to high bandw idth. the spread spectrum characterisitics are : maximum of 0.5%, 30 to 33khz modulation frequency, linear profile. 5. measured with scope averaging on to find mean v alue. 6. long-term variation from nominal of input-to-ou tput skew over temperature and voltage for a single device. 7. this parameter is measured at the outputs of two separate 9fg1901h devices driven by a single ck410 b+. the 9fg1901h must be set to high bandwidth. differential phase jitter is the accumulation of th e phase jitter not shared by the outputs (eg. not i ncluding the affects of spread spectrum). target r anges of consideration are agents with bw of 1-22mhz and 11- 33mhz.
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 14 electrical characteristics - phase jitter parameter symbol conditions min typ. max units notes t jphpcie1 pcie gen 1 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz ) 42/41 86 ps 1,2,3,5 t jphfbd1_3.2g fbd refclk phase jitter (including pll bw 11 - 33 mhz, = 0.54, td=12 ns ftrl=0.2mhz) 2.8/2.7 3 ps (rms) 1,2 t jphfbd1_4.8g fbd refclk phase jitter (including pll bw 11 - 33 mhz, = 0.54, td=12 ns ftrl=0.2mhz) 2.4/2.1 2.5 ps (rms) 1,2 notes on phase jitter: 2 device driven by 932s421bglf or equivalent 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1 -12 4 hi-bandwidth number/low bandwidth number with spre ad on. spread off gives lower numbers. 5 byte 9 must be properly set to meet these paramete rs. 1 see http://www.pcisig.com for complete specs. guar anteed by design and characterization, not tested i n production. jitter, phase
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 15 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 16 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt tm frequency gearing clock for cpu, pci e gen1 & fbd 1386a - 02/02/10 9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 17 e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e symbol 72l n 72 a 0.8 1.0 n d 18 a1 0 0.05 n e 18 a3 b 0.18 0.3 e d x e basic d2 min. / max. 5.75 6.15 e2 min. / max. 5.75 6.15 l min. / max. 0.3 0.5 max. 0.25 reference 0.50 basic 10.00 x 10.00 dimensions thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions (mm) symbol min. ordering information part / order number shipping packaging package tempera ture 9FG1901HKLF tubes 72-pin mlf 0 to +70 c 9FG1901HKLFt tape and reel 72-pin mlf 0 to +70 c ?lf? suffix to the part numbers are the pb-free con figuration and are rohs compliant. ?h? is the device revision designator (will not cor relate to the datasheet revision).
9fg1901h frequency gearing clock for cpu, pcie gen1 & fbd 18 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and jap an integrated device t echnology singapore (1997) pte. lt d. reg. no. 199707558g 435 orchard road #20-03 w isma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett w ood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify product s or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 9/8/2008 initial release - 0.2 1/22/2009 1. updated skews, phase jitter, smbus address graph ic 2. removed output divider table. 3. re-ordered smbus and electrical tables for consi stency. various a 2/2/2010 released to final.

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